An EEPROM (Electrically Erasable and Programmable ROM) that is a type of memory LSI comprises a constant voltage generating circuit for applying a voltage (Vpp) Higher than a power supply voltage (Vcc) to a gate electrode when rewriting (writing and erasing) data. A zener diode as a clamp element for voltage stabilization is connected to the boosting circuit in the constant voltage generating circuit, whereby the rewrite voltage (Vpp) is constantly supplied to the EEPROM. A publicly known zener diode of such type is disclosed in Japanese Patent Laid-open No. 64-59949, dated Mar. 7, 1989, for example.
The zener diode described in the above-mentioned Laid-open No. 64-59949 is composed of: an n+ type semiconductor region formed in a p type well of a semiconductor substrate; and a p+ type semiconductor region formed in a p type well at a lower part of this n+ type semiconductor region. An area surrounding a planar pattern on the p+ type semiconductor region is smaller than that of the n+ type semiconductor region, and the p+ type semiconductor region is located so as to be substantially centered to that of the n+ type semiconductor region. In this manner, the p+ type semiconductor region and n+ type semiconductor region have such a structure as is closed in the semiconductor substrate, so that the structure can prevent an occurrence of a problem with a leakage current due to an interface level of an interface between the semiconductor substrate and an insulation film (silicon oxide film) on an upper part thereof.
To the p+ type well in which the above p+ type semiconductor region is formed and the n+ type semiconductor region is formed thereon, a wire is connected through a connection hole provided in an insulation film that covers upper parts of both. To the n+ type semiconductor region, a wire is connected through the center thereof, i.e., a connection hole formed at the insulation film located in the upper part of the p+ type semiconductor region.